pwm_internal.h

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#ifndef PWM_INTERNAL_H
#define PWM_INTERNAL_H

#define PWM_BASE_ADDR_PHYS  (peripheralsBaseAddressPhys+0x20c000)
#define PWM_AREA_LEN        0x28


#define PWM_REG_CTL_OFF         0x0
#define PWM_REG_CTL_ADDR_PHYS       (PWM_REG_CTL_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_STA_OFF         0x4
#define PWM_REG_STA_ADDR_PHYS       (PWM_REG_STA_OFF + PWM_BASE_ADDR_PHYS

#define PWM_REG_DMAC_OFF        0x8
#define PWM_REG_DMAC_ADDR_PHYS  (PWM_REG_DMAC_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_RNG1_OFF        0x10
#define PWM_REG_RNG1_ADDR_PHYS  (PWM_REG_RNG1_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_DAT1_OFF        0x14
#define PWM_REG_DAT1_ADDR_PHYS  (PWM_REG_DAT1_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_FIF1_OFF        0x18
#define PWM_REG_FIF1_ADDR_PHYS  (PWM_REG_FIF1_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_RNG2_OFF        0x20
#define PWM_REG_RNG2_ADDR_PHYS  (PWM_REG_RNG2_OFF + PWM_BASE_ADDR_PHYS)

#define PWM_REG_DAT2_OFF        0x24
#define PWM_REG_DAT2_ADDR_PHYS  (PWM_REG_DAT2_OFF + PWM_BASE_ADDR_PHYS)



//::::REG_CTL : Control::::::::::::::::::::::::::::::::::::
//----Channel 1----
#define CTL_PWEN1_MASK  0x1
#define CTL_MODE1_MASK  (1<<1)
#define CTL_RPTL1_MASK  (1<<2)
#define CTL_SBIT1_MASK  (1<<3)
#define CTL_POLA1_MASK  (1<<4)
#define CTL_USEF1_MASK  (1<<5)
#define CTL_CLRF_MASK   (1<<6)
#define CTL_MSEN1_MASK  (1<<7)
//----Channel 2----
#define CTL_PWEN2_MASK  (1<<8)
#define CTL_MODE2_MASK  (1<<9)
#define CTL_RPTL2_MASK  (1<<10)
#define CTL_SBIT2_MASK  (1<<11)
#define CTL_POLA2_MASK  (1<<12)
#define CTL_USEF2_MASK  (1<<13)
#define CTL_MSEN2_MASK  (1<<15)

//::::REG_STA : Status::::::::::::::::::::::::::::::::::::::
#define STA_FULL1_MASK  0x1
#define STA_EMPT1_MASK  (1<<1)
#define STA_WERR1_MASK  (1<<2)
#define STA_RERR1_MASK  (1<<3)
#define STA_GAPO1_MASK  (1<<4)
#define STA_GAPO2_MASK  (1<<5)
#define STA_GAPO3_MASK  (1<<6)
#define STA_GAPO4_MASK  (1<<7)
#define STA_BERR_MASK   (1<<8)
#define STA_STA1_MASK   (1<<9)
#define STA_STA2_MASK   (1<<10)
#define STA_STA3_MASK   (1<<11)
#define STA_STA4_MASK   (1<<12)


//::::REG_DMAC : DMA Configuration::::::::::::::::::::::::::
#define DMAC_DREQ_MASK  (0xFF)
#define DMAC_PANIC_MASK (0xFF<<8)
#define DMAC_ENAB_MASK  (0x1<<31)


//::::REG_RNG1 : Channel 1 Range::::::::::::::::::::::::::::
#define RNG1_PWM_RNG1_MASK 0xFFFFFFFF

//::::REG_DAT1 : Channel 1 Data:::::::::::::::::::::::::::::
#define PWM_DAT1_MASK   0xFFFFFFFF


//::::REG_FIF1 : Fifo input:::::::::::::::::::::::::::::::::
#define FIF1_PWM_FIFO_MASK 0xFFFFFFFF


//::::REG_RNG2 : Channel 2 Range::::::::::::::::::::::::::::
#define RNG1_PWM_RNG2_MASK 0xFFFFFFFF

//::::REG_DAT2 : Channel 2 Data:::::::::::::::::::::::::::::
#define PWM_DAT2_MASK   0xFFFFFFFF


#endif // PWM_INTERNAL_H