dma.h

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#ifndef DMA_H
#define DMA_H

#include <stdint.h>
#include <stdlib.h>
#include "../memoryManagement/cacheCoherentMemoryProvider.h"



//::::::::::::::::::::::: Masks and offsets for the Transfer Info register ::::::::::::::::::::::::::::::::::::::::::::::::

    #define TI_NO_WIDE_BURSTS_OFF                   26
    #define TI_NO_WIDE_BURSTS_MASK              (1<<TI_NO_WIDE_BURSTS_OFF)


    #define TI_WAITS_OFF                        21
    #define TI_WAITS_MASK                       (31<<TI_WAITS_OFF)


    #define TI_PERMAP_OFF                       16
    #define TI_PERMAP_MASK                      (31<<TI_PERMAP_OFF)


    #define TI_BURST_LEN_OFF                    12
    #define TI_BURST_LEN_MASK                   (0xf<<TI_BURST_LEN_OFF)


    #define TI_SRC_IGNORE_OFF                   11
    #define TI_SRC_IGNORE_MASK                  (1<<TI_SRC_IGNORE_OFF)


    #define TI_SRC_DREQ_OFF                     10
    #define TI_SRC_DREQ_MASK                    (1<<TI_SRC_DREQ_OFF)


    #define TI_SRC_WIDTH_OFF                    9
    #define TI_SRC_WIDTH_MASK                   (1<<TI_SRC_WIDTH_OFF)


    #define TI_SRC_INC_OFF                      8
    #define TI_SRC_INC_MASK                     (1<<TI_SRC_INC_OFF)


    #define TI_DEST_IGNORE_OFF                  7
    #define TI_DEST_IGNORE_MASK                 (1<<TI_DEST_IGNORE_OFF)


    #define TI_DEST_DREQ_OFF                    6
    #define TI_DEST_DREQ_MASK                   (1<<TI_DEST_DREQ_OFF)


    #define TI_DEST_WIDTH_OFF                   5
    #define TI_DEST_WIDTH_MASK                  (1<<TI_DEST_WIDTH_OFF)


    #define TI_DEST_INC_OFF                     4
    #define TI_DEST_INC_MASK                    (1<<TI_DEST_INC_OFF)


    #define TI_WAIT_RESP_OFF                    3
    #define TI_WAIT_RESP_MASK                   (1<<TI_WAIT_RESP_OFF)


    #define TI_2DMODE_OFF                       1
    #define TI_2DMODE_MASK                      (1<<TI_2DMODE_OFF)


    #define TI_INTEN_OFF                        (0)
    #define TI_INTEN_MASK                       (1)


    #define DREQ_ALWAYS_ON      0
    #define DREQ_DSI            1
    #define DREQ_PCM_TX     2
    #define DREQ_PCM_RX     3
    #define DREQ_SMI            4
    #define DREQ_PWM            5
    #define DREQ_SPI_TX     6
    #define DREQ_SPI_RX     7



//:::::::::::::::::::::::::::::: Masks and offsets for the Transfer Length register :::::::::::::::::::::::::::::::::::::::

    #define TL_Y_LEN_OFF    16
    #define TL_Y_LEN_MASK   (0x3fff<<TL_Y_LEN_OFF)


    #define TL_X_LEN_OFF    0
    #define TL_X_LEN_MASK   (0xffff)


    #define TL_LEN_OFF  0
    #define TL_LEN_MASK (0x3fffffff)



//::::::::::::::::::::::::::::::: Masks and offsets for the 2DStride Register :::::::::::::::::::::::::::::::::::::::::::::

    #define REG_2D_STRIDE_DST_STRIDE_OFF    16
    #define REG_2D_STRIDE_DST_STRIDE_MASK   (0xffff<<REG_2D_STRIDE_DST_STRIDE_OFF)


    #define REG_2D_STRIDE_SRC_STRIDE_OFF    0
    #define REG_2D_STRIDE_SRC_STRIDE_MASK   (0xffff)




typedef volatile struct ControlBlock_struct
{
    uint32_t    transferInfo;
    uint32_t    srcAddrPhys;
    uint32_t    dstAddrPhys;
    uint32_t    transferLength;
    uint32_t    _2DStrideMode;
    uint32_t    nextControlBlockAddrPhys;
    uint32_t    zero1;
    uint32_t    zero2;
} ControlBlock;



int dma_init();

int dma_isInit();

int dma_channelResetInitDefault(int channel);

int dma_setControlBlockAddr(int channel, uint32_t controlBlockAddrPhys);

int dma_writeControlBlock(ControlBlock* cb,uintptr_t srcAddrPhys,uintptr_t dstAddrPhys,size_t transferLength,uintptr_t nextControlBlockPhys,uint32_t transferInfo,uint32_t _2DStrideModeInfo,size_t _2DStrideTransferLenX,size_t _2DStrideTransferLenY);

int dma_allocControlBlockPhys(uintptr_t srcAddrPhys,uintptr_t dstAddrPhys,size_t transferLength,uintptr_t nextControlBlockPhys,uint32_t transferInfo,uint32_t _2DStrideModeInfo,size_t _2DStrideTransferLenX,size_t _2DStrideTransferLenY,Ccmb_desc* area);

int dma_dumpRegisters(int channel, char* s);

int dma_printRegisters(int channel);

int dma_printControlBlock(ControlBlock* cb);

int dma_controlBlockToString(ControlBlock* cb, char* s);

int dma_setChannelActive(int channel, int value);

int dma_setChannelGlobalEnable(int channel, int value);

uint32_t dma_getUsableChannels();

int dma_isChannelActive(int channel);

int dma_dumpRegistersDense(int channel, char* s);


//this tells doxygen to ignore the static assert
static_assert(sizeof(ControlBlock)==32, "ControlBlock has wrong size");


#endif